CH1The whole stack
Measured on a running DHO924S: 217 MB of its 3.9 GB of RAM in use, with the UI the biggest process at about 97 MB and the acquisition engine at about 22 MB. There is no Android runtime, no Java, no X server and no Wayland compositor. All the scope software is written in Rust. Every layer's version and licence, down to each package and crate, is on What's inside NovaOS.
Why 6.12
The newest stable kernel is 7.2, and we could run it. We don't, because the GPU matters more: 6.12 is the newest kernel in Rockchip's BSP that ships the Mali vendor driver (libmali), and on these scopes it beat the open-source Panfrost driver in our tests. 6.12 is also a long-term kernel, supported upstream until December 2028 according to kernel.org. When Rockchip moves its Mali support to a newer kernel, NovaOS moves with it.
The kernel itself is our own port: Rockchip's latest 6.12 BSP merged with the current 6.12 long-term release, plus the board support for these scopes (device trees, the FPGA's PCIe and SPI paths, the panel, the front panel), written and maintained by us rather than taken from another board's or distribution's kernel. That gives these scopes Rockchip's drivers and the upstream security fixes together. We're not aware of another RK3399 kernel that combines the two.
CH2Pixels: GLES straight to KMS
The UI is the only DRM master of the panel. It renders with OpenGL ES on the Mali-T860, using the vendor Mali driver, and page-flips with KMS: no display server, no window manager, no compositor between the trace and the glass. The boot splash uses the same path, so the panel goes from boot screen to live trace without flicker or a console in between.
- Trace drawing: the Mali driver uploads only about 110 MB/s, so the UI reduces each waveform to per-pixel-column min/max lines on the CPU and sends a quarter of the bytes in one upload per frame.
- Density display: the engine counts every acquired waveform into per-pixel maps; the UI adds the new counts to one texture per frame and grades it on the GPU.
- Thread placement: the render thread is pinned to one Cortex-A72 and acquisition to the other, with density counting spread over all six cores. On the same screen, the A72 drew 45 frames a second where an A53 managed 38, with about a quarter less CPU per frame.
CH3Samples: PCIe DMA to a zero-copy ring
The FPGA streams records over PCIe through Xilinx's XDMA driver into the engine, which publishes batches in a shared-memory ring. The UI reads them under a per-slot sequence lock with no copy and no socket in between; a batch the engine reuses before it is read is simply skipped, so the engine never waits on the screen. Settings and results travel on a small Unix-socket protocol.
CH4Remote view: GPU to hardware encoder
When another display watches, the UI converts each frame to NV12 on the GPU and reads it back asynchronously, and the host daemon feeds it to the RK3399's hardware H.264 encoder through Rockchip MPP, then sends it over a WebSocket. A change on the scope reaches the network in about 78 ms and another display's glass in about 0.1 s,.
Kept small on purpose
- The network-facing service runs sandboxed under systemd: its own user, a read-only view of the system and a restricted set of system calls.
- Quiet on the flash: settings are written only when they change, and the calibration partition is mounted read-only.
- Updates are signed bundles; the new root sits beside the old one and rolls back by itself if it fails to boot.
- One image for two families: the DHO and the MHO run the same root filesystem, byte for byte. Each model's hardware differences live in its device tree and its tables of limits.
Numbers measured on our own DHO924S and MHO934 in October 2026. More in the boot write-up.